1. Field of the Invention
The present invention relates to a memory module that realizes a desired memory capacity using a plurality of memory chips. More particularly, the invention relates to a memory module offering a high yield and reduced costs, a method for control of that memory module, and a method for setting a fault bit table for use with that memory module.
2. Prior Art
Memory chips made of semiconductor integrated circuits are known to develop fault bits for diverse reasons during their production process.
The presence of fault bits is circumvented conventionally by equipping individual memory chips with redundant circuits. To compensate for the fault bits, a laser trimming machine commonly called a wafer processor is used at wafer die sort time to cut polycrystal Si or Al parts by laser melting and to connect polycrystal Si parts for conduction by later annealing while each memory chip is being tested.
One disadvantage of the above prior art measure is that wafer processors are very expensive (they often cost a few hundred million yen per unit).
Another disadvantage of the prior art is a poor throughput due to the fact that the fault bits are compensated while the addresses of each memory chip are being tested sequentially. In the case of a one-megabit DRAM (dynamic random access memory), it typically takes several minutes to compensate for the fault addresses of each chip by wafer processor.
Most memories are supplied and used in the form of memory modules (including memory boards and memory cards). Conventionally, memory modules are each composed of the necessary number of fault-free chips. One defective memory chip within a module means a totally disabled address area of that memory chip. In many cases, the module containing even one defective chip is discarded in total as useless. Therefore usually the memory module consists of only good chips.
A solution to the above problem of one chip disabling the entire module is disclosed by Japanese Patent Laid Open No. 61-180350. The disclosure involves adding at least one reserve memory chip to the memory module so that if a memory chip therein malfunctions, the defective chip is replaced by a reserve chip. The setup is called a field programmable logic array (FPLA).
Another solution to the problem above is disclosed by Japanese Patent Laid-Open No. 3-191450. The disclosure proposes furnishing a plurality of memory chips including at least one reserve chip amounting to N chips that constitute the memory module. In operation, only n chips (n&lt;N) are used. If a faulty chip develops among the operating chips, that faulty chip is replaced by one of the remaining fault-free chips (N-n).
Both of the above solutions involve replacing each faulty chip with one good memory chip. Considering the fact that even a faulty memory chip contains numerous parts that are still good, the waste involved is enormous. Needless to say, all memory chips replacing the defective must be entirely fault-free chips.